Shift registers are widely used in a scanning signal line driving circuit and a data signal line driving circuit of a liquid crystal display apparatus, for example, in order to generate a scanning signal to be supplied to each scanning signal line, or in order to take timing for sampling each data signal from a video signal. Such scanning signal line driving circuits and data signal line driving circuits using shift registers are disclosed, for example, in Japanese Publication of Unexamined Patent Application, Tokukai, No. 2000-322020 (published on Nov. 24, 2000; corresponding to counterpart U.S. patent application Ser. No. 09/568,889), Japanese Publication of Unexamined Patent Application, Tokukai, No. 2000-339984 (published on Dec. 8, 2000; corresponding to counterpart U.S. patent application Ser. No. 09/578,440), and Japanese Publication of Unexamined Patent Application, Tokukai, No. 2001-307495 (published on Nov. 2, 2001; corresponding to counterpart U.S. patent application Ser. No. 09/703,918).
Meanwhile, power consumption of an electronic circuit is increased in proportion to a frequency, a load capacitance, and square of a voltage. Thus, for attaining lower power consumption, there is a trend to set a driving voltage lower and lower in the liquid crystal display apparatus itself and in a circuit to be connected to the liquid crystal display apparatus, such as a circuit for generating the video signal that is to be supplied to the liquid crystal display apparatus.
However, for example in pixel circuits, a scanning signal line driving circuit, and a data signal line driving circuit, and the like circuit, which are composed of polycrystal silicon thin file transistor so that a wide display area can be attained, difference between threshold voltages may become as high as several volts ([V]) between substrates or even within a substrate. Therefore, the driving voltage includes such a margin as to absorb effect of the difference between the threshold voltages. Thus, the driving voltage has not been lowered enough. On the other hand, the driving voltage is set, for example, at 5[V], 3.3[V] or even lower values in a circuit using a single crystal silicon transistor, such as the generating circuit for the video signal.
Therefore, a display panel receives, from an external circuit such as the generating circuit for the video signal, a start pulse lower than that of the driving voltage of a shift register. In this case, the shift register is provided with a level shifter for boosting the start pulse. Specifically, for example as demonstrated by a shift register 1 shown in FIG. 12, a level shifter 3 is provided in an input side of a shift register section 2. With this arrangement, a start pulse SP, which is supplied from the generating circuit for the video signal, and which has an amplitude as low as 5[V] as described above, is boosted to be a start pulse SPO (which is a driving voltage of the shift register section 2) having an amplitude as high as 15[V], so that the start pulse SPO is supplied to a first-stage flip-flop f1 of the shift register section 2.
The first-stage flip-flop f1 transmits the thus boosted start pulse SPO to a flip-flop f2, which is a next stage to the flip-flop f1, in synchronism with a clock signal CK supplied from the generating circuit for the video signal. Similar operations are sequentially performed through flip-flops f1, f2, . . . fn-1, and fn, which are connected each other in series. The flip-flops f1, f2, . . . fn-1, and fn sequentially output a selection pulse as output signals s1, s2, . . . , sn-1, and sn.
FIG. 13 is a block diagram showing an example of an arrangement of the level shifter 3. The level shifter 3 is provided with a pair of NMOS transistors n1 and n2, a pair of PMOS transistors p1 and p2, and two stages of invertors inv1 and inv2. The NMOS transistors n1 and n2 have gates, which are connected with each other, and drains, which are respectively connected with drains of the PMOS transistors p1 and p2. A source of the NMOS transistor n1 is grounded. Meanwhile, the gate and drain of the NMOS transistor n1 are connected with each other. A source of the NMOS transistor n2 receives the start pulse SP. Sources of the PMOS transistors p1 and p2 are commonly supplied with a high level driving voltage Vcc as high as 15[V], while gates thereof are commonly grounded.
Therefore, an output terminal that is a node between the drain of the PMOS transistor p2 and that of the NMOS transistor n2 outputs the start pulse SP, which has been inputted to the source of the NMOS transistor n2 and boosted to the driving voltage Vcc. The output is amplified by the two stages of the inverter inv1 and inv2, and then outputted as the start pulse SPO, which is thus boosted and is not inverted.
In the level shifter 3 arranged as above, the NMOS transistors n1 and n2, and the PMOS transistors p1 and p2 constitute a level shifter section of a current driving type. Thus, whether or not the start pulse SP is inputted, the PMOS transistors p1 and p2 are ON always, whereby the gates of the NMOS transistors n1 and n2 become high level so that the NMOS transistors n1 and n2 are ON always and let a current flow through themselves. Therefore, it is possible to boost the start pulse SP without any problem even if the start pulse SP has an amplitude lower than a threshold voltage of the NMOS transistor n2.
On the other hand, in a level shifter of a voltage driving type, in which an input switching element is switched (turned) ON and OFF in accordance with a level of an input signal, it is impossible to carry out such boosting when the start pulse SP has an amplitude lower than a threshold voltage of input switching element. However, the level shifter of the current driving type disadvantageously has high power consumption because the current is flowing through the level shifter of this type always.